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INTEGRATED CIRCUITS
74ABT16501A 74ABTH16501A 18-bit universal bus transceiver (3-State)
Product specification Supersedes data of 1997 Jun 12 IC23 Data Handbook 1998 Feb 27
Philips Semiconductors
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ABT16501A 74ABTH16501A
FEATURES
* 18-bit bidirectional bus interface * 3-State buffers * Output capability: +64mA/-32mA * TTL input and output switching levels * 74ABTH16501A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused inputs
DESCRIPTION
The 74ABT16501A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CPAB. When OEAB is High, the outputs are active. When OEAB is Low, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active High, and OEBA is active Low). Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Two options are available, 74ABT16501A which does not have the bus-hold feature and 74ABTH16501A which incorporates the bus-hold feature.
* Live insertion/extraction permitted * Power-up reset * Power-up 3-State * Positive edge-triggered clock inputs * Latch-up protection exceeds 500mA per JEDEC Std 17 * ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
* Flexible operation permits 18 embedded D-type latches or
flip-flops to operate in clocked, transparent, and latched modes.
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN CI/O ICCZ ICCL PARAMETER Propagation delay An to Bn or Bn to An Input capacitance (Control pins) I/O pin capacitance Quiescent supply current CONDITIONS Tamb = 25C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC Outputs disabled; VI/O = 0V or VCC Outputs disabled; VCC = 5.5V Outputs low; VCC = 5.5V TYPICAL 2.2 1.8 3 7 500 9 UNIT ns pF pF A mA
ORDERING INFORMATION
PACKAGES 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74ABT16501A DL 74ABT16501A DGG 74ABTH16501A DL 74ABTH16501A DGG NORTH AMERICA BT16501A DL BT16501A DGG BH16501A DL BH16501A DGG DWG NUMBER SOT371-1 SOT364-1 SOT371-1 SOT364-1
1998 Feb 27
2
853-1788 19027
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ABT16501A 74ABTH16501A
LOGIC SYMBOL
30 28 27 55 2 1
PIN CONFIGURATION
OEAB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND CPAB B0 GND B1 B2 VCC B3 B4 B5 GND B6 B7 B8 B9 B10 B11 GND B12 B13 B14 VCC B15 B16 GND B17 CPBA GND
54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26
LEAB A0 GND A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND
OEBA
OEAB
CPBA
LEBA
LEAB
CPAB
SA00127
A12 A13 A14
PIN DESCRIPTION
PIN NUMBER 1 27 2, 28 55,30 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 4, 11, 18, 25, 32, 39, 46, 53 7, 22, 35, 50 SYMBOL OEAB OEBA LEAB/LEBA CPAB/ CPBA A0-A17 NAME AND FUNCTION A-to-B Output enable input B-to-A Output enable input (active low) A-to-B/B-to-A Latch enable input A-to-B/B-to-A Clock input (active rising edge) Data inputs/outputs (A side)
VCC A15 A16 GND A17 OEBA LEBA
SA00128
B0-B17
Data inputs/outputs (B side) Ground (0V) Positive supply voltage
GND VCC
1998 Feb 27
3
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ABT16501A 74ABTH16501A
LOGIC SYMBOL (IEEE/IEC)
OEAB CPAB LEAB
1 55 2
EN1 2C3 C3 G2
OEBA CPBA LEBA
27 30 28
EN4 5C6 C6 G5
A0
3
3D 4
1 1
1 6D
54
B0
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26
52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17
SA00129
1998 Feb 27
4
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ABT16501A 74ABTH16501A
FUNCTION TABLE
INPUTS OEAB L L L L L L H H H H H H H H LEAB H L L L H H L L L L CPAB X X X H or L X X X X H or L H or L An X h I X h I H L h I h I X X X H L NC H L H L H L H L H L Internal Registers OUTPUTS OPERATING MODE Bn Z Z Disabled, Disabled Latch data Z Z Z Disabled, Disabled Clock data Z H Trans arent Transparent L H Latch data & dis lay display L H Clock data & display dis lay L H Hold data & display dis lay L NOTE: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA. H = High voltage level h = High voltage level one set-up time prior to the Enable or Clock transition L = Low voltage level I = Low voltage level one set-up time prior to the Enable or Clock transition NC= No Change X = Don't care Z = High Impedance "off" state = High-to-Low Enable or Clock transition = Low-to-High Clock transition Disabled, Hold data Disabled
1998 Feb 27
5
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ABT16501A 74ABTH16501A
LOGIC DIAGRAM
OEAB
1
CLKAB 55
LEAB 2
LEBA
28
CLKBA 30
OEBA 27
A1
3
ID C1 CLK ID C1 CLK
54 B1
To 17 other channels
SW00235
1998 Feb 27
6
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ABT16501A 74ABTH16501A
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IO OUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 Output in Off or High state Output in Low state DC output current Output in High state Storage temperature range -64 -65 to +150 C VI < 0 CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 128 mA UNIT V mA V mA V
DC output diode current DC output voltage3
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate; Outputs enabled Operating free-air temperature range -40 PARAMETER MIN 4.5 0 2.0 0.8 -32 64 10 +85 MAX 5.5 VCC V V V V mA mA ns/V C UNIT
1998 Feb 27
7
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ABT16501A 74ABTH16501A
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C MIN VIK Input clamp voltage VCC = 4.5V; IIK = -18mA VCC = 4.5V; IOH = -3mA; VI = VIL or VIH VOH High-level output voltage VCC = 5.0V; IOH = -3mA; VI = VIL or VIH VCC = 4.5V; IOH = -32mA; VI = VIL or VIH VOL VRST II Low-level output voltage Power-up output voltage3 Input leakage current Bus Hold B H ld current A and B t d ports5 74ABTH16501A Power-off leakage current Power-up/down 3-State output current4 3-State output High current 3-State output Low current Output High leakage current Output current1 VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IO = 1mA; VI = GND or VCC VCC = 5.5V; VI = GND or 5.5V VCC = 4.5V; VI = 0.8V IHOLD VCC = 4.5V; VI = 2.0V VCC = 5.5V; VI = 0 to 5.5V IOFF IPU/PD IIH + IOZH IIL + IOZL ICEX IO ICCH ICCL ICCZ ICC Additional supply current per input pin2 74ABT16501A Additional supply current per input pin2 74ABTH16501A Quiescent supply current VCC = 0.0V; VO or VI 4.5V VCC = 2.1V; VO = 0.0V or VCC; VI = GND or VCC; VOE = Don't care VCC = 5.5V; VO = 5.5V; VI = VIL or VIH VCC = 5.5V; VO = 0.0V; VI = VIL or VIH VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND -50 Control pins 35 -75 800 "2 "2 1.0 -1.0 2.0 -80 0.5 9 0.5 100 50 10 -10 50 -180 2 19 2 -50 100 50 10 -10 50 -180 2 19 2 A A A A A mA mA mA mA A 2.5 3.0 2.0 TYP -0.8 2.9 4.0 2.4 0.35 0.13 "0.01 0.55 0.55 1.0 35 -75 A MAX -1.2 2.5 3.0 2.0 0.55 0.55 1.0 Tamb = -40C to +85C MIN MAX -1.2 V V V V V V A UNIT
5.0
50
50
ICC
200
500
500
A
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V 10% a transition time of up to 100sec is permitted. 5. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 27
8
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ABT16501A 74ABTH16501A
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum clock frequency Propagation delay An to Bn or Bn to An Propagation delay LEAB to Bn or LEBA to An Propagation delay CPAB to Bn or CPBA to An Output enable time to HIGH and LOW level Output disable time from HIGH and LOW level 1 2 3 1 5 6 5 6 150 1.0 1.0 1.5 1.4 1.6 1.4 1.1 1.0 1.3 1.0 Tamb = +25oC VCC = +5.0V TYP 225 2.2 1.8 3.2 2.9 3.5 2.9 3.0 2.4 3.3 2.4 3.0 2.5 4.3 3.8 4.5 3.8 4.0 3.4 4.3 3.4 MAX Tamb = -40 to +85oC VCC = +5.0V 0.5V MIN 150 1.0 1.0 1.5 1.4 1.6 1.4 1.1 1.0 1.3 1.0 3.5 3.0 5.0 4.2 5.0 4.2 4.7 3.9 5.3 3.9 MAX MHz ns ns ns ns ns UNIT
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25oC VCC = +5.0V MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw tw(H) Setup time, HIGH or LOW An to CPAB or Bn to CPBA Hold time, HIGH or LOW An to CPAB or Bn to CPBA Setup time, HIGH or LOW An to LEAB or Bn to LEBA Hold time HIGH or LOW An to LEAB or Bn to LEBA Pulse width, HIGH or LOW CPAB or CPBA Pulse width, HIGH LEAB or LEBA 4 4 4 4 1 3 2.0 2.0 0.7 0.7 2.0 2.0 0.7 0.7 3 3 TYP 0.5 0.5 -0.5 -0.5 0.5 0.4 -0.4 -0.5 1.9 1.2 Tamb = -40 to +85oC VCC = +5.0V 0.5V MIN 2.0 2.0 0.7 0.7 2.0 2.0 0.7 0.7 3 3 ns ns ns ns ns ns UNIT
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
1/fMAX An or Bn CPBA or CPAB VM VM tPLH tW(L) tPHL An or Bn VM tW(H) tPLH VM VM VOL tPHL VOH VM VM
An or Bn VM
SA00132 SA00131
Waveform 2. Propagation Delay, Transparent Mode
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency
1998 Feb 27
9
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ABT16501A 74ABTH16501A
AC WAVEFORMS (Continued)
VM = 1.5V, VIN = GND to 3.0V
OEBA LEAB or LEBA VM VM VM OEAB tPLH VOH An or Bn VM VM An or Bn VOL SA00133 VM tPZH tPHZ VOH VOH -0.3V VM VM
tW(H) tPHL
SA00135
Waveform 3. Propagation Delay, Enable to Output, and Enable Pulse Width
Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level
CPAB or CPBA, LEAB or LEBA
Note: The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUIT AND WAVEFORMS
VCC 7.0V RL 90% NEGATIVE PULSE VM 10% tTHL (tF) CL RL POSITIVE PULSE 10% tW tTLH (tR) 90% 90% VM 10% 0V 10% 0V tTLH (tR) tTHL (tF) AMP (V) tW VM 90% AMP (V)
PULSE GENERATOR
SWITCH POSITION
TEST tPLZ tPZL All other SWITCH closed closed open
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
1998 Feb 27
EEE EEEEE EEE EEE EEEEE EEE EEE EEEEE EEE
VM VM VM VM tS(H) th(H) tS(L) th(L) VM VM
An or Bn
OEBA VM OEAB VM
tPZL An or Bn VM
tPLZ
VOL +0.3V VOL
SA00134
SA00136
Waveform 4. Data Setup and Hold Times
Waveform 6. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
VIN D.U.T. RT
VOUT
Test Circuit for 3-State Outputs
VM
VM = 1.5V Input Pulse Definition
INPUT PULSE REQUIREMENTS FAMILY Amplitude 74ABT/H16 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns
SA00018
10
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ABT16501A 74ABTH16501A
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
1998 Feb 27
11
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ABT16501A 74ABTH16501A
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
1998 Feb 27
12
Philips Semiconductors
Product specification
74ABT16501A 74ABTH16501A
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-03494
Philips Semiconductors
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